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Features
* Single 2.7V - 3.6V Supply * Dual-interface Architecture
- RapidSTM Serial Interface: 50 MHz Maximum Clock Frequency (SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz) - Rapid8TM 8-bit Interface: 20 MHz Maximum Clock Frequency Page Program - 16,384 Pages (1,056 Bytes/Page) Main Memory Sector Erase Architecture - Sixty-three 270,336-byte Sectors - One 261,888-byte Sector - One 8,488-byte Sector Two 1056-byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming the Flash Array Continuous Read Capability through Entire Array - Ideal for Code Shadowing Applications Low-power Dissipation - 10 mA Active Read Current Typical - Serial Interface - 12 mA Active Read Current Typical - 8-bit Interface - 15 A CMOS Standby Current Typical Hardware Data Protection Security: 128-byte Security Register - 64-byte User Programmable Space - Unique 64-byte Device Identifier JEDEC Standard Manufacturer and Device ID Read 100 Program/Erase Cycles Per Sector Minimum Data Retention - 10 Years Commercial Temperature Range
* *
* * *
* * * * * *
128-megabit 2.7-volt Dual-interface Code Shadow DataFlash(R) AT45CS1282 Preliminary
Description
The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for infrequent code shadowing applications. This device utilizes Atmel's e-STACTM Multi-Level Cell (MLC) memory technology, which allows a single cell to
TM
Pin Configurations
Pin Name CS SCK/CLK SI SO I/O7 - I/O0 WP RESET RDY/BUSY SER/BYTE Function Chip Select Serial Clock/Clock Serial Input Serial Output 8-bit Input/Output Hardware Page Write Protect Pin
TSOP Top View: Type 1
NC NC RDY/BUSY RESET WP NC NC NC VCC GND NC NC NC NC CS SCK SI* SO* NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC NC NC NC I/O7* I/O6* I/O5* I/O4* VCCP* GNDP* I/O3* I/O2* I/O1* I/O0* SER/BYTE* CLK NC NC NC
CBGA Top View
1 2 3 4 5
A
Chip Reset Ready/Busy Serial/8-bit Interface Control
B C
NC SER/BYTE NC I/O7 VCC I/O6 I/O5 I/O4
D
I/O2 SCK/CLK GND
E
I/O1 CS RDY/BUSY WP SO SI
F
I/O0 RESET I/O3 NC NC
G
NC GNDP VCCP
H
Note:
*Optional Use - See pin description text for connection information.
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store two bits of information delivering a very cost effective high density Flash memory. The AT45CS1282 supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for frequencies up to 33 MHz. The dual-interface allows a dedicated serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller or vice versa. However, the use of either interface is purely optional. Its 138,412,032 bits of memory are organized as 16,384 pages of 1,056 bytes each. In addition to the 132-megabit main memory, the AT45CS1282 also contains two SRAM buffers of 1,056 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial applications where high-density, low-pin count, low-voltage and low-power are essential. The device operates at clock frequencies up to 50 MHz with a typical active read current consumption of 10 mA. To allow for simple in-system reprogrammability, the AT45CS1282 does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45CS1282 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK). All programming and erase cycles are self-timed.
Block Diagram
WP FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 1 (1056 BYTES)
BUFFER 2 (1056 BYTES)
SCK/CLK CS RESET VCC GND RDY/BUSY SER/BYTE
I/O INTERFACE
SI
SO
I/O7 - I/O0
Memory Array
To provide optimal flexibility, the memory array of the AT45CS1282 is divided into two levels of granularity comprising of sectors, and pages. The "Memory Architecture Diagram" illustrates the breakdown of each level and details the number of pages per sector. All program operations to the DataFlash occur on a page by page basis. The erase operations is performed at the sector level.
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Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages 8,448 bytes (8K + 256)
PAGE ARCHITECTURE
8 Pages
PAGE 0 PAGE 1
SECTOR 0b = 248 Pages 261,888 bytes (248K + 7,936) PAGE 6 PAGE 7 SECTOR 1 = 256 Pages 270,336 bytes (256K + 8K) PAGE 8 PAGE 9
SECTOR 2 = 256 Pages 270,336 bytes (256K + 8K)
PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18
SECTOR 62 = 256 Pages 270,336 bytes (256K + 8K)
SECTOR 63 = 256 Pages 270,336 bytes (256K + 8K)
PAGE 16,382 PAGE 16,383
Page = 1,056 bytes (1K + 32)
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main memory address location through either the SI (serial input) pin or the 8-bit input pins (I/O7 - I/O0). All instructions, addresses, and data are transferred with the most significant bit (MSB) first. Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to denote the 11 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA13 - PA0 and BA10 - BA0, where PA13 - PA0 denotes the 14 address bits required to designate a page address and BA10 - BA0 denotes the 11 address bits required to designate a byte address within the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS and Rapid8 protocols for Mode 0 and Mode 3. Please refer to the "Detailed Bit-level Read Timing" diagrams in this datasheet for details on the clock cycle sequences for each mode. CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of E8H must be clocked into the device followed by four address bytes (which comprises 7 don't care bits plus the 25-bit page and byte address sequence) and a series of don't care clock cycles (24 if using the serial interface or 19 if using the 8-bit interface). The first 14 bits (PA13 - PA0) of the 3
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25-bit address sequence specify which page of the main memory array to read, and the last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte address within the page. The 24 or 19 don't care clock cycles that follow the four address bytes are needed to initialize the read operation. Following the don't care clock cycles, additional clock pulses on the SCK/CLK pin will result in data being output on either the SO (serial output) pin or the eight output pins (I/O7- I/O0). The CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit (or byte if using the 8-bit interface mode) in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Continuous Array Read is defined by the fCAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. MAIN MEMORY PAGE READ: A main memory page read allows the user to read data directly from any one of the 16384 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of D2H must be clocked into the device followed by four address bytes (which comprise 7 don't care bits plus the 25-bit page and byte address sequence) and a series of don't care clock cycles (24 if using the serial interface or 19 if using the 8-bit interface). The first 14 bits (PA13 - PA0) of the 25-bit address sequence specify the page in main memory to be read, and the last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte address within that page. The 24 or 19 don't care clock cycles that follow the four address bytes are sent to initialize the read operation. Following the don't care bytes, additional pulses on SCK/CLK result in data being output on either the SO (serial output) pin or the eight output pins (I/O7 - I/O0). The CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main Memory Page Read is defined by the fSCK specification. The Main Memory Page Read bypasses both data buffers and leaves the contents of the buffers unchanged. BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. With the serial interface, an opcode of D4H is used to read data from buffer 1, and an opcode of D6H is used to read data from buffer 2. Likewise with the 8-bit interface an opcode of 54H is used to read data from buffer 1 and an opcode of 56H is used to read data from buffer 2. To perform a buffer read, the opcode must be clocked into the device followed by four address bytes comprised of 21 don't care bits and 11 buffer address bits (BFA10 - BFA0). Following the four address bytes, additional don't care bytes (one byte if using the serial interface or two bytes if using the 8-bit interface) must be clocked in to initialize the read operation. Since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bytes, the don't care bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pins (SO or I/O7 - I/O0). 4
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Program and Erase Commands
BUFFER WRITE: Data can be clocked in from the input pins (SI or I/O7 - I/O0) into either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by four address bytes comprised of 21 don't care bits and 11 buffer address bits (BFA10 - BFA0). The 11 buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin. BUFFER TO MAIN MEMORY PAGE PROGRAM: A previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. The programming time is selectable by the system through the use of different opcodes between a normal mode and a fast mode (the fast program option will consume more current). A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2 (98H for buffer 1 fast program or 99H for buffer 2 fast program), must be clocked into the device followed by four address bytes consisting of 7 don't care bits, 14-page address bits (PA13 - PA0) that specify the page in the main memory to be written and 11 don't care bits. When a low-tohigh transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously erased using the sector erase commands. The programming of the page is internally self-timed and should take place in a maximum time of tP for normal programming or tFP for fast programming. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. SECTOR ERASE: The Sector Erase command can be used to individually erase any sector in the main memory. There are 65 sectors and only one sector can be erased at one time. Sector 0a requires a different opcode than sectors 0b-63. To perform a sector 0a erase, an opcode of 50h must be loaded into the device, followed by four address bytes comprised of 7 don't care bits, 11-page address bits (PA13 - PA3) and 14 don't care bits. To perform a sector 0b-63 erase, an opcode of 7Ch must be loaded into the device, followed by four address bytes comprised of 7 don't care bits, 6-page address bits (PA13 - PA8) and 19 don't care bits. The 6-page address bits are used to specify which sector is to be erased. Refer to Sector Erase addressing table. When a low-tohigh transition occurs on the CS pin, the part will erase the selected sector. The erase operation is internally self-timed and should take place in a maximum time of tSE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
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Sector Erase Addressing
PA13 0 0 0 0 * * * 1 1 1 1 PA12 0 0 0 0 * * * 1 1 1 1 PA11 0 0 0 0 * * * 1 1 1 1 PA10 0 0 0 0 * * * 1 1 1 1 PA9 0 0 0 1 * * * 0 0 1 1 PA8 0 0 1 0 * * * 0 1 0 1 PA7 0 X X X * * * X X X X PA6 0 X X X * * * X X X X PA5 0 X X X * * * X X X X PA4 0 X X X * * * X X X X PA3 0 X X X * * * X X X X PA2 X X X X * * * X X X X PA1 X X X X * * * X X X X PA0 X X X X * * * X X X X Sector 0a 0b 1 2 * * * 60 61 62 63
Additional Commands
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed by four address bytes comprised of 7 don't care bits, 14-page address bits (PA13- PA0), which specify the page in main memory that is to be transferred, and 11 don't care bits. The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the address bytes from the input pins (SI or I/O7 - I/O0). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read or the RDY/BUSY can be monitored to determine whether the transfer has been completed. MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation, a 1-byte opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed by four address bytes consisting of 7 don't care bits, 14-page address bits (PA13 - PA0) that specify the page in the main memory that is to be compared to the buffer, and 11 don't care bits. The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the address bytes from the input pins (SI or I/O7 - I/O0). On the low-to-high transition of the CS pin, the 1056 bytes in the selected main memory page will be compared with the 1056 bytes in buffer 1 or buffer 2. During this time (t XFR ), the status register and the RDY/BUSY pin will indicate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare. STATUS REGISTER READ: The status register can be used to determine the device's ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode must be loaded into the device. After the opcode and optional dummy byte(s) is clocked in, the 1-byte status register will be clocked out on the output pins (SO or I/O7 - I/O0), starting with the next clock cycle. In case of serial interface, opcode D7H is followed with an optional dummy byte (8 clocks). For Serial applications over 25 MHz, opcode must be always followed with a dummy byte. In case of applications with 8-bit interface, opcode D7H and two dummy clock cycles should be used. When using the serial interface, the data in the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next eight clock cycles.
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The six most-significant bits of the status register will contain device information, while the remaining two least-significant bits are reserved for future use and will have undefined values. After the one byte of the status register has been clocked out, the sequence will repeat itself (as long as CS remains low and SCK/CLK is being toggled). The data in the status register is constantly updated, so each repeating sequence will output new data. Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. Since the data in the status register is constantly updated, the user must toggle SCK/CLK pin to check the ready/busy status. There are four operations that can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program and Sector Erase. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the AT45CS1282, the four bits are 0, 1, 0, 0. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The device density is not the same as the density code indicated in the JEDEC device ID information. The device density is provided only for backward compatibility.
Status Register Format
Bit 7 RDY/BUSY Bit 6 COMP Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 0 Bit 1 X Bit 0 X
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Manufacturer and Device ID Read
This instruction conforms to the JEDEC standard and allows the user to read the Manufacturer ID, Device ID, and Extended Device Information. This mode is only offered via the serial interface with clock frequencies up to 25 MHz. A 1-byte opcode, 9FH, must be clocked into the device while the CS pin is low. After the opcode is clocked in, the Manufacturer ID, 2 bytes of Device ID and Extended Device Information will be clocked out on the SO pin. The fourth byte of the sequence output is the Extended Device Information String Length byte. This byte is used to signify how many bytes of Extended Device Information will be output.
Manufacturer and Device ID Information
Byte 1 - Manufacturer ID
JEDEC Assigned Code Hex Value 1FH Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 Manufacturer ID 1FH = Atmel
Byte 2 - Device ID (Part 1)
Family Code Hex Value 29H Bit 7 0 Bit 6 0 Bit 5 1 Bit 4 0 Bit 3 1 Density Code Bit 2 0 Bit 1 0 Bit 0 1 Family Code Density Code 001 = DataFlash 01001 = 128-Mbit
Byte 3 - Device ID (Part 2)
MLC Code Hex Value 20H Bit 7 0 Bit 6 0 Bit 5 1 Bit 4 0 Product Version Code Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 MLC Code Product Version 001 = 2-Bit/Cell Technology 00000 = Initial Version
Byte 4 - Extended Device Information String Length
Byte Count Hex Value 00H Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Byte Count 00H = 0 Bytes of Information
CS
SI
9FH Opcode
SO
1FH
Manufacturer ID Byte n
29H
Device ID Byte 1
20H
Device ID Byte 2
00H
Extended Device Information String Length
Data
Extended Device Information Byte x
Data
Extended Device Information Byte x + 1
This information would only be output if the Extended Device Information String Length value was something other than 00H.
Each transition represents 8 bits
Note:
Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a "Continuation Code" and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte.
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Security Register
The AT45CS1282 contains a specialized register that can be used for security purposes in system design. The Security Register is a unique 128-byte register that is divided into two portions. The first 64 bytes (byte 0 to byte 63) of this register are allocated as a onetime user programmable space. Once these 64 bytes have been programmed, they should not be reprogrammed. The remaining 64 bytes of this register (byte 64 to byte 127) are factory programmed by Atmel and will contain a unique number for each device. The factory programmed data is fixed and cannot be changed. The Security Register can be read by clocking in opcode 77H to the device followed by four address bytes (which are comprised of 21 don't care bits plus 11 byte address bits) and a series of don't care clock cycles (24 if using the serial interface and 19 if using the 8-bit interface). The Security Register Read can be terminated by asserting CS low to high after the 128-byte security register has been read out. The continuation of clocking past that will result in indeterminate data on the output. See the opcode table on page 13 for this mode. To program the first 64 bytes of the Security Register, a two step sequence must be used. The first step requires that the user loads the desired data into Buffer 1 by using the Buffer 1 Write operation (opcode 84H - see Buffer Write description). The user should specify the starting buffer address as location zero and should write a full 64 bytes of information into the buffer. Otherwise, the first 64 bytes of the buffer may contain data that was previously stored in the buffer. It is not necessary to fill the remaining 992 bytes (byte locations 64 through 1055) of the buffer with data. After the Buffer 1 Write operation has been completed, the Security Register can be subsequently programmed by reselecting the device and clocking in opcode 9AH into the device followed by four don't care bytes (32 clock cycles if using the serial interface and four clock cycles if using the 8-bit interface). After the final don't care clock cycle has been completed, a low-to-high transition on the CS pin will cause the device to initiate an internally self-timed program operation in which the contents of Buffer 1 will be programmed into the Security Register. Only the first 64 bytes of data in Buffer 1 will be programmed into the Security Register; the remaining 992 bytes of the buffer will be ignored. The Security Register program operation should take place in a maximum time of tP.
Operation Mode Summary
The modes described can be separated into two groups - modes that make use of the Flash memory array (Group A) and modes that do not make use of the Flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2. Continuous Array Read 3. Main Memory Page to Buffer 1 (or 2) Transfer 4. Main Memory Page to Buffer 1 (or 2) Compare 5. Buffer 1 (or 2) to Main Memory Page Program 6. Sector 0a Erase 7. Sector 0b-63 Erase Group B modes consist of: 1. Buffer 1 (or 2) Read 2. Buffer 1 (or 2) Write 3. Status Register Read
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If a Group A mode is in progress (not fully completed), then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started, except the first two Group A commands (Memory Array Read Commands). This gives the DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 ("Using Atmel's Serial DataFlash") for more details.
Pin Descriptions
SERIAL/8-BIT INTERFACE CONTROL (SER/BYTE): The DataFlash may be configured to utilize either its serial port or 8-bit port through the use of the serial/8-bit control pin (SER/BYTE). When the SER/BYTE pin is held high, the serial port (SI and SO) of the DataFlash will be used for all data transfers, and the 8-bit port (I/O7 - I/O0) will be in a high impedance state. Any data presented on the 8-bit port while SER/BYTE is held high will be ignored. When the SER/BYTE is held low, the 8-bit port will be used for all data transfers, and the SO pin of the serial port will be in a high impedance state. While SER/BYTE is low, any data presented on the SI pin will be ignored. Switching between the serial port and 8-bit port should only be done while the CS pin is high and the device is not busy in an internally self-timed operation. The SER/BYTE pin is internally pulled high; therefore, if the 8-bit port is never to be used, then connection of the SER/BYTE pin is not necessary. In addition, if the SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally, then the 8-bit input/output pins (I/O7-I/O0), the VCCP pin, and the GNDP pin should be treated as "don't connects". SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into the device. The SI pin is used for all data input, including opcodes and address sequences. If the SER/BYTE pin is always driven low, then the SI pin should be a "don't connect". SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data serially out from the device. If the SER/BYTE pin is always driven low, then the SO pin should be a "don't connect". 8-BIT INPUT/OUTPUT (I/O7-I/O0): The I/O7-I/O0 pins are bidirectional and used to clock data into and out of the device. The I/O7-I/O0 pins are used for all data input, including opcodes and address sequences. The use of these pins is optional, and the pins should be treated as "don't connects" if the SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally. SERIAL CLOCK/CLOCK (SCK/CLK): The SCK and CLK pins are input-only pins and are used to control the flow of data to and from the DataFlash. The SCK and CLK pins are used for serial and 8-bit interface respectively. Data is always clocked into the device on the rising edge of SCK/CLK and clocked out of the device on the falling edge of SCK/CLK. CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not selected, data will not be accepted on the input pins (SI or I/O7-I/O0), and the output pins (SO or I/O7-I/O0) will remain in a high impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition on the CS pin is required to end an operation. HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages (sectors 0 and 1) of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program
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commands previously mentioned. If this pin and feature are not utilized it is recommended that the WP pin be driven high externally. RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally. READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. 8-BIT PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP pins are used to supply power for the 8-bit input/output pins (I/O7-I/O0). The VCCP and GNDP pins need to be used if the 8-bit port is to be utilized; however, these pins should be treated as "don't connects" if the SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started. The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip select CS pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, 8 I/Os and chip select CS pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.
System Considerations
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3447A-DFLSH-2/04
Table 1. Read Commands
Command Main Memory Page Read Continuous Array Read Buffer 1 Read Buffer 2 Read Buffer 1 Read Buffer 2 Read Serial/8-bit Both Both Serial Serial 8-bit 8-bit Opcode D2h E8h D4h D6h 54h 56h
Table 2. Program and Erase Commands
Command Buffer 1 Write Buffer 2 Write Buffer 1 to Main Memory Page Program Buffer 1 to Main Memory Page Program, Fast Program Buffer 2 to Main Memory Page Program Buffer 2 to Main Memory Page Program, Fast Program Sector 0a Erase Sector 0b-63 Erase Serial/8-bit Both Both Both Both Both Both Both Both Opcode 84h 87h 88h 98h 89h 99h 50h 7Ch
Table 3. Additional Commands
Command Main Memory Page to Buffer 1 Transfer Main Memory Page to Buffer 2 Transfer Main Memory Page to Buffer 1 Compare Main Memory Page to Buffer 2 Compare Status Register Read Manufacturer and Device ID Read Security Register Program
(1)
Serial/8-bit Both Both Both Both Both Serial Both
Opcode 53h 55h 60h 61h D7h 9Fh 9Ah
Security Register Read Both 77h Note: 1. The Security Register Program command utilizes data stored in Buffer 1. Therefore, this command must be used in conjunction with the Buffer 1 write command. See the Security Register description for details.
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AT45CS1282 [Preliminary]
Table 4. Detailed Bit-level Addressing Sequence
Address Byte Address Byte Address Byte Address Byte
Opcode 50h 53h 54h 55h 56h 60h 61h 77h 7Ch 84h 87h 88h 89h 98h 99h 9Ah 9Fh D2h D4h D6h D7h E8h
Opcode
Additional Don't Care Bytes* N/A N/A 2* N/A 2* N/A N/A 3 or 19* N/A N/A N/A N/A N/A N/A N/A N/A N/A 3 or 19* 1 1 1/0 or 1* 3 or 19*
PA10
BA10
PA13
PA12
PA11
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
01010000 01010011 01010100 01010101 01010110 01100000 01100001 01110111 01111100 10000100 10000111 10001000 10001001 10011000 10011001 10011010 10011111 11010010 11010100 11010110 11010111 11101000
xxxxxxxP xxxxxxxP xxxxxxxx xxxxxxxP xxxxxxxx xxxxxxxP xxxxxxxP xxxxxxxx xxxxxxxP xxxxxxxx xxxxxxxx xxxxxxxP xxxxxxxP xxxxxxxP xxxxxxxP xxxxxxxx N/A xxxxxxxP xxxxxxxx xxxxxxxx N/A xxxxxxxP
PPPPPPPP PPxxxxxx PPPPPPPP PPPPPxxx xxxxxxxx
xxxxxxxx xxxxxxxx
xxxxxBBB BBBBBBBB xxxxxxxx
PPPPPPPP PPPPPxxx xxxxxxxx
xxxxxBBB BBBBBBBB xxxxxxxx xxxxxxxx
PPPPPPPP PPPPPxxx PPPPPPPP PPPPPxxx xxxxxxxx PPPPPxxx xxxxxxxx xxxxxxxx
xxxxxBBB BBBBBBBB xxxxxxxx xxxxxxxx
xxxxxBBB BBBBBBBB xxxxxBBB BBBBBBBB xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx N/A
PPPPPPPP PPPPPxxx PPPPPPPP PPPPPxxx PPPPPPPP PPPPPxxx PPPPPPPP PPPPPxxx xxxxxxxx N/A xxxxxxxx N/A
PPPPPPPP PPPPPBBB BBBBBBBB xxxxxxxx xxxxxxxx N/A xxxxxBBB BBBBBBBB xxxxxBBB BBBBBBBB N/A N/A
PPPPPPPP PPPPPBBB BBBBBBBB
Notes:
P = Page Address Bit B = Byte/Buffer Address Bit x = Don't Care *The number with (*) is for 8-bit interface.
BA0
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
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3447A-DFLSH-2/04
Absolute Maximum Ratings*
Temperature under Bias ............................... -55 C to +125 C Storage Temperature .................................... -65 C to +150 C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC Operating Range
AT45CS1282 Operating Temperature (Case) VCC Power Supply Note:
(1)
Com.
0 C to 70 C 2.7V to 3.6V
1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started.
DC Characteristics
Symbol ISB ICC1(1) ICC2(2) ICC3 ICC4 ICC5 ILI ILO VIL VIH VOL VOH Notes: Parameter Standby Current Active Current, Read Operation, Serial Interface Active Current, Read Operation, 8-bit Interface Active Current, Program Operation, Page Program Active Current, Program Operation, Fast Page Program Active Current, Sector Erase Operation Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = 2.7V IOH = -100 A VCC - 0.2V VCC x 0.7 0.4 Condition CS, RESET, WP = VIH, all inputs at CMOS levels f = 20 MHz; IOUT = 0 mA; VCC = 3.6V f = 10 MHz; IOUT = 0 mA; VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VIN = CMOS levels VI/O = CMOS levels Min Typ 15 10 12 Max 50 20 20 50 65 50 1 1 VCC x 0.3 Units A mA mA mA mA mA A A V V V V
1. ICC1 during a buffer read is 25 mA maximum. 2. ICC2 during a buffer read is 25 mA maximum.
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AT45CS1282 [Preliminary]
AC Characteristics - RapidS Serial Interface
Symbol fSCK fCAR tWH tWL tCS tCSS tCSH tCSB tSU tH tHO tDIS tV tXFR tP tFP tSE0a tSE0b-63 tRST tREC Parameter SCK Frequency SCK Frequency for Continuous Array Read SCK High Time SCK Low Time Minimum CS High Time CS Setup Time CS Hold Time CS High to RDY/BUSY Low Data In Setup Time Data In Hold Time Output Hold Time Output Disable Time Output Valid Page to Buffer Transfer/Compare Time Page Programming Time Fast Page Programming Time Sector 0a Erase Time Sector 0b-63 Erase Time RESET Pulse Width RESET Recovery Time 10 1 50 15 75 2 200 4 5 7 2 10 10 500 9 9 250 250 250 150 Min Typ Max 50 40 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns s ms ms ms s s s
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3447A-DFLSH-2/04
AC Characteristics - Rapid8 8-bit Interface
Symbol fSCK1 fCAR1 tWH tWL tCS tCSS tCSH tCSB tSU tH tHO tDIS tV tXFR tP tFP tSE0a tSE0b-63 tRST tREC Parameter CLK Frequency CLK Frequency for Continuous Array Read CLK High Time CLK Low Time Minimum CS High Time CS Setup Time CS Hold Time CS High to RDY/BUSY Low Data In Setup Time Data In Hold Time Output Hold Time Output Disable Time Output Valid Page to Buffer Transfer/Compare Time Page Programming Time Fast Page Programming Time Sector 0a Erase Time Sector 0b-63 Erase Time RESET Pulse Width RESET Recovery Time 10 1 50 15 75 2 200 4 10 10 3 15 15 500 16 16 250 250 250 150 Min Typ Max 20 20 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns s ms ms ms s s s
Input Test Waveforms and Measurement Levels
AC DRIVING LEVELS 2.4V 1.5V AC MEASUREMENT LEVEL
0.45V tR, tF < 2 ns (10% to 90%)
Output Test Load
DEVICE UNDER TEST 30 pF
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AT45CS1282 [Preliminary]
3447A-DFLSH-2/04
AT45CS1282 [Preliminary]
AC Waveforms
Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK/CLK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK/CLK signal is still low (SCK/CLK low time is specified as tWL). Timing waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 33 MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid over the full frequency range (maximum frequency = 50 MHz) of the RapidS serial case. Waveform 5 and waveform 6 are for 8-bit Rapid8 interface over the full frequency range of operation (maximum frequency = 20 MHz).
Waveform 1 - SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
tCS CS tCSS SCK/CLK tV SO HIGH IMPEDANCE tSU SI VALID IN tH tHO VALID OUT tDIS HIGH IMPEDANCE tWH tWL tCSH
Waveform 2 - SPI Mode 3 Compatible (for Frequencies up to 33 MHz)
tCS CS tCSS SCK/CLK tV SO HIGH Z tSU SI VALID IN tHO VALID OUT tH tDIS HIGH IMPEDANCE tWL tWH tCSH
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3447A-DFLSH-2/04
Waveform 3 - RapidS Mode 0 (for all Frequencies)
tCS
CS
tCSS
SCK/CLK
tWH
tWL
tCSH
tV
SO HIGH IMPEDANCE
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
tSU
SI VALID IN
tH
Waveform 4 - RapidS Mode 3 (for all Frequencies)
tCS
CS
tCSS
SCK/CLK
tWL
tWH
tCSH
tV
SO HIGH Z
tHO
VALID OUT
tDIS
HIGH IMPEDANCE
tSU
SI VALID IN
tH
Waveform 5 - Rapid8 Mode 0 (FMAX = 20 MHz)
tCS CS tCSS SCK/CLK tV I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) HIGH IMPEDANCE tSU VALID IN tH tHO VALID OUT tDIS HIGH IMPEDANCE tWH tWL tCSH
Waveform 6 - Rapid8 Mode 3 (FMAX = 20 MHz)
tCS CS tCSS SCK/CLK tV I/O7 - I/O0 (OUTPUT) I/O7 - I/O0 (INPUT) HIGH Z tSU VALID IN tHO VALID OUT tH tDIS HIGH IMPEDANCE tWL tWH tCSH
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AT45CS1282 [Preliminary]
3447A-DFLSH-2/04
AT45CS1282 [Preliminary]
Reset Timing
CS
tREC tCSS
SCK/CLK
tRST
RESET HIGH IMPEDANCE SO or I/O7 - I/O0 (OUTPUT) SI or I/O7 - I/O0 (INPUT) HIGH IMPEDANCE
Note:
The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (Except Status Register Read, Manufacturer and Device ID Read)
SI or I/O7 - I/O0 (INPUT) MSB XXXX XXXX 7 Bits Don't Care CMD 8 bits 8 bits 8 bits 8 bits
XXXX XXXX Page Address (PA13 - PA0)
XXXX XXXX
XXXX XXXX
LSB
Byte/Buffer Address (BA10 - BA0/BFA10 - BFA0)
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 1 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 TO MAIN MEMORY PAGE PROGRAM
BUFFER 1 (1056 BYTES)
BUFFER 1 WRITE
BUFFER 2 (1056 BYTES)
BUFFER 2 WRITE
I/O INTERFACE
SI
I/O7 - I/O0
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3447A-DFLSH-2/04
Buffer Write
* Completes writing into selected buffer
CS SI or I/O7 - I/O0 (INPUT)
CMD
X
X
X***X, BFA10-8
BFA7-0
n
n+1
Last Byte
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS SI or I/O7 - I/O0 (INPUT)
CMD XXXXXXX PA13 PA12-5 PA4-0, XXX X***X
Each transition represents 8 bits
n = 1st byte n+1 = 2nd byte
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
MAIN MEMORY PAGE TO BUFFER 1 MAIN MEMORY PAGE TO BUFFER 2
BUFFER 1 (1056 BYTES)
BUFFER 1 READ
BUFFER 2 (1056 BYTES)
MAIN MEMORY PAGE READ BUFFER 2 READ
I/O INTERFACE
SO
I/O7 - I/O0
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AT45CS1282 [Preliminary]
Main Memory Page Read
CS
SI or I/O7 - I/O0 (INPUT)
CMD
xxx...PA13
PA12-5
PA4-0, BA10-8
BA7-0
X 24 Cycles for Serial 19 Cycles for Parallel
X
SO or I/O7 - I/O0 (OUTPUT)
n
n+1
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer CS
SI or I/O7 - I/O0 (INPUT)
CMD
XX...PA13
PA12-5
PA4-0, XXX
X
SO or I/O7 - I/O0 (OUTPUT)
Buffer Read
CS I/O7-I/O0 (INPUT)
CMD X X
X***X, BFA10-8 BFA7-0
X
ADDR I/O7-I/O0 (OUTPUT)
ADDR 1 Dummy Byte (Serial) 2 Dummy Bytes (Parallel)
n n+1
Each transition represents 8 bits
n = 1st byte read n+1 = 2nd byte read
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3447A-DFLSH-2/04
Detailed Bit-level Read Timing - RapidS Serial Interface Mode 0
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
62
63
64
65
66
67
tSU
SI
1 1 X X X
tV
SO HIGH IMPEDANCE
DATA OUT
D7 D6 D5 D2 D1
LSB D0
MSB D7 D6 D5
BIT 8,447 OF PAGE n
BIT 0 OF PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK tSU
1
2
3
4
5
60
61
62
63
64
65
66
67
COMMAND OPCODE SI
1 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
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AT45CS1282 [Preliminary]
Detailed Bit-level Read Timing - RapidS Serial Interface Mode 0 (Continued) Buffer Read (Opcode: D4H or D6H)
CS
SCK tSU
1
2
3
4
5
44
45
46
47
48
49
50
51
COMMAND OPCODE SI
1 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Status Register Read (Opcode: D7H)
CS
SCK tSU SI
1
2
3
4
5
6
7
8
9
10
11
12
15
16
COMMAND OPCODE
1 1 0 1 0 1 1 1
tV SO HIGH IMPEDANCE
D7 MSB
tV STATUS REGISTER OUTPUT
D6 D5 D4 D1 D0 LSB D7 MSB
DON'T CARE FOR FREQ. OVER 25 MHz
Manufacturer and Device ID Read (Opcode: 9FH)
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
16
17
COMMAND OPCODE SI
1 00 1 1 1 1 1
tV SO HIGH IMPEDANCE
0 MSB 0
PRODUCT ID OUTPUT
0 1 1 LSB 0 MSB 0
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3447A-DFLSH-2/04
Detailed Bit-level Read Timing - RapidS Serial Interface Mode 3
Continuous Array Read (Opcode: E8H)
CS
SCK
1
2
63
64
65
66
67
tSU
SI
1 1 X X X
tV
SO HIGH IMPEDANCE
DATA OUT
D7 D6 D5 D2 D1
LSB D0
MSB D7 D6 D5
BIT 8,447 OF PAGE n
BIT 0 OF PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
SCK tSU
1
2
3
4
5
61
62
63
64
65
66
67
68
COMMAND OPCODE SI
1 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
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AT45CS1282 [Preliminary]
Detailed Bit-level Read Timing - RapidS Serial Interface Mode 3 (Continued)
Buffer Read (Opcode: D4H or D6H)
CS
SCK tSU
1
2
3
4
5
45
46
47
48
49
50
51
52
COMMAND OPCODE SI
1 1 0 1 0 X X X X X
tV SO HIGH IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Status Register Read (Opcode: D7H)
CS
SCK tSU SI
1
2
3
4
5
6
7
8
9
10
11
12
17
18
COMMAND OPCODE
1 1 0 1 0 1 1 1
tV SO HIGH IMPEDANCE
tV STATUS REGISTER OUTPUT
D7 MSB D6 D5 D4 D0 LSB D7 MSB D6
DON'T CARE FOR FREQ. OVER 25 MHz
Manufacturer and Device ID Read (Opcode: 9FH)
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
17
18
COMMAND OPCODE SI
1 0 0 1 1 1 1 1
tV SO HIGH IMPEDANCE
0 MSB 0
PRODUCT ID OUTPUT
0 1 1 LSB 0 MSB 0
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3447A-DFLSH-2/04
Detailed 8-bit Read Timing - Rapid8 Mode 0
Continuous Array Read (Opcode: E8H)
CS
CLK
1
2
22
23
24
25
26
27
tSU
I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
CMD ADDR X X X
tV
HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA DATA DATA DATA DATA DATA
BYTE 1055 OF PAGE n
BYTE 0 OF PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
5
20
21
22
23
24
25
26
27
COMMAND OPCODE
CMD ADDR ADDR ADDR ADDR X X X X X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA
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AT45CS1282 [Preliminary]
Detailed 8-bit Timing - Rapid8 Mode 0 (Continued)
Buffer Read (Opcode: 54H or 56H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
5
6
7
8
COMMAND OPCODE
CMD X X ADDR ADDR X X
tV HIGH IMPEDANCE DATA OUT
DATA DATA DATA MSB
Status Register Read (Opcode: D7H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
CMD
tV HIGH IMPEDANCE
X X DATA DATA DATA
STATUS REGISTER OUTPUT
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3447A-DFLSH-2/04
Detailed 8-bit Read Timing - Rapid8 Mode 3
Continuous Array Read (Opcode: E8H)
CS
CLK
1
2
23
24
25
26
27
tSU
I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
CMD ADDR X X X
tV
HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA DATA DATA DATA DATA DATA
BYTE 1055 OF PAGE n
BYTE 0 OF PAGE n+1
Main Memory Page Read (Opcode: D2H)
CS
CLK tSU I/07-I/O0 (INPUT) I/07-I/O0 (OUTPUT)
1
2
3
4
5
21
22
23
24
25
26
27
28
COMMAND OPCODE
CMD ADDR ADDR ADDR ADDR X X X X X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA DATA
28
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3447A-DFLSH-2/04
AT45CS1282 [Preliminary]
Detailed 8-bit Read Timing - Rapid8 Mode 3 (Continued)
Buffer Read (Opcode: 54H or 56H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
4
5
6
7
8
9
10
CMD
X
X
ADDR ADDR
X
X
tV HIGH IMPEDANCE
DATA OUT
DATA DATA DATA
Status Register Read (Opcode: D7H)
CS
CLK tSU I/O7-I/O0 (INPUT) I/O7-I/O0 (OUTPUT)
1
2
3
CMD
tV HIGH IMPEDANCE
X X DATA DATA
STATUS REGISTER OUTPUT
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3447A-DFLSH-2/04
Ordering Information
fSCK (MHz) 50(1) 50(1) Note: ICC (mA) Active 20(1) 20(1) Standby 0.05 0.05
Ordering Code Package
Operation Range Commercial (0 C to 70 C) Commercial (0 C to 70 C)
AT45CS1282-TC AT45CS1282-CC
40T 44C2
1. RapidS Serial Interface.
Package Type 40T 44C2 40-lead, (10 x 20 mm) Plastic Thin Small Outline Package, Type I (TSOP) 44-ball, (8 x 12 mm) Plastic Chip-size Ball Grid Array Package (CBGA)
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AT45CS1282 [Preliminary]
Packaging Information
40T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 9.90 0.50 NOM - - 1.00 20.00 18.40 10.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 10.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40T, 40-lead (10 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 40T REV. B
R
31
3447A-DFLSH-2/04
44C2 - CBGA
D
0.12 C C Seating Plane
Marked A1 Identifier
E
Side View
Top View
A1 A
2.00 REF
5 4
D1
3 2 1
A1 Ball Corner
A
e
B C D
E1
E F G H J
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 D MIN - 0.25 7.90 NOM - - 8.00 4.00 TYP 11.90 12.00 8.00 TYP 1.00 TYP 0.40 TYP 12.10 MAX 1.20 - 8.10 NOTE
2.00 REF e Ob
D1 E E1
Bottom View
e
Ob
06/10/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 44C2, 44-ball (5 x 9 Array), 8 x 12 x 1.2 mm Body, 0.4 mm Ball Plastic Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 44C2 REV. A
R
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Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
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Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
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Asia
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ASIC/ASSP/Smart Cards
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Japan
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Literature Requests
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof, and DataFlash (R) are the registered trademarks, and RapidS TM, Rapid8 TM and e -STAC TM are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
3447A-DFLSH-2/04 /xM

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